With the advent of the technology to fabricate integrated circuits, it becomes a trend to scale down the geometry size of semiconductor devices and increases the density of semiconductor devices per unit area of a silicon wafer. Electrostatic discharge (ESD) protection is an important issue for the design of integrated circuits. Electrostatic discharge is also a significant problem of the fabrication of integrated circuits. Such as, human or machine handling of the semiconductor wafer or chip during the assembly or processing of a wafer could produce electrostatic charges in integrated circuits. These electrostatic charges will cause destructive electrostatic pulse to destroy devices in integrated circuits.
As the development in the formation of sub-micron semiconductor technologies has been quite modest in comparison, the thickness of the gate oxide and the length of the device's channel have become thinner or shorter than ever. The failure susceptibility of integrated circuits to ESD protection increases due to the IC fabrication towards sub-micron feature lengths.
Typically, input/output signals to a metal oxide semiconductor (MOS) are input into or output from input/output pads. The input/output pads are generally connected to the gates of MOS devices. All pins for input/output of MOS IC must be protected by ESD protective circuits to prevent harmful static discharge voltages from damaging the IC.
Referring to FIG. 1, it is demonstrated an electrostatic discharge (ESD) circuit of integrated circuits. The ESD circuit is consisted of several first pairs that each of the first pairs further comprises a used NMOS device and a used PMOS device, and several second pairs, that each of the second pairs further comprises a unused NMOS device and a unused PMOS device. The ESD circuit is connected between an internal circuit 2000 and a pad 1000.
Referring to FIG. 1 again, a used PMOS device P1 and a used NMOS device N1 are connected together for discharging. Besides, a used PMOS device P2 and a used NMOS device N2 are coupled together for discharging. In detail, the gates of the PMOS P1, the NMOS N1, the PMOS P2 and the NMOS N2 are coupled together and with the internal circuit 2000. The sources of the PMOS P1 and the PMOS P2 are coupled with a power line V.sub.cc. The sources of the NMOS N1 and the NMOS N2 are coupled with ground. In addition, the drains of the PMOS P1, the PMOS P2, the NMOS N1 and the NMOS N2 are coupled together and these drains are coupled with the pad 1000.
Referring to FIG. 1 again, a unused PMOS device P3, a unused NMOS device N3, a unused PMOS device P4 and a unused NMOS device N4 are coupled together and these devices are functionless during the discharging of the internal circuit 2000. The drains of the PMOS device P3, the PMOS device P4, the NMOS device N3 and the NMOS device N4 are coupled together with the pad 1000. Besides, the sources of the PMOS device P3 and the PMOS device P4 are coupled with the power line V.sub.cc, and the source of the NMOS device N3 and the NMOS device N4 are coupled with ground. The gates of the PMOS device P3 and the PMOS device P4 are coupled with the power line V.sub.cc through a resistor RP3 and RP4, respectively. Besides, the gates of the NMOS device N3 and the NMOS device N4 are coupled with ground through a resistor RN3 and RN4, respectively.
Referring to FIG. 1, the power line V.sub.cc provides a voltage bias for the PMOS devices P1, P2, P3 and P4. Static charges are conducted from the internal circuit 2000 to ground through the NMOS devices N1 and N2.
Referring to FIG. 2, it is demonstrated a cross-section view of an NMOS device. The NMOS device has a gate oxide 110 on a substrate 100 and a gate 120 is formed on the gate oxide 110. Two N-type source/drain regions 200 and 210 are formed in the substrate 100 adjacent to the gate oxide 110. Besides, spacers 130 are formed on the sidewalls of the gate oxide 110 and the gate 120 and two N-type light doped drain (LDD) 220 are formed in the substrate 100 below the spacers 130. A positive power line V.sub.D is connected to one of the source/drain regions 200 to serve as a drain region and a power line V.sub.ss is connected to another one of the source/drain regions 210 to act as a source region. In this figure, a typical structure of an NMOS device is shown.
In general, the power line V.sub.ss of an NMOS device is connected to ground. When a voltage difference is applied between the gate 120 and the power line V.sub.D, the fermi-energy band E.sub.F of the metal region A is raised. Furthermore, the voltage different includes a horizontal electrical field E.sub.h 300 and a vertical electrical field E.sub.v 310 and the vertical electrical field E.sub.v is applied to the N-type light doped drain regions 220. Referring to FIG. 3, it shows an energy-band diagram of an NMOS device during a positive voltage is applied on the gate. In this figure, the metal region of an NMOS device is in the region A, the oxide region of this is in the region B and the semiconductor region of this is in the region C. The semiconductor region C has four energy bands to represent the energy-band characteristic of the region. The energy bands include an eigen-energy band E.sub.i, a conducting-energy band E.sub.C, a Fermi-energy band E.sub.F and a valence-energy band E.sub.v. When a positive voltage difference is applied on the metal region A, the valence band of the region C is raised. The valence band in the interface state between the region B and the region C may be higher than the conduction band of the region A. Thus, electrons on the interface state can move from the valence band to the conduction band and these electrons flow out from the drain. This phenomenon is indicated as the band-to-band tunneling. As electrons move from the valence band to the conduction band, electrical holes are produced at the same time. The holes will be accelerated by the horizontal electrical field E.sub.h 300 and these holes become hot carriers. Additionally, the energy of the hot carriers is high enough to tunnel through the region B, the oxide layer, and into the region A. The hot carriers will accumulate on the gate region. Therefore, electrons can easily cross over the barrier layer in the region B from the region A to the region C.
Referring to FIG. 4, it demonstrates a curve that is the relation of the gate voltage V.sub.g to the drain current I.sub.d in an NMOS device. As the gate voltage V.sub.g is less than -0.3 volts, the drain current I.sub.d raises up and it is indicated as a band-to-band tunneling current. That is, the band-to-band tunneling current is a flow of the electrons, which are on the interface state, through the energy gap between the valence band and the conduction band into the drain. Simultaneously, some electrical holes are produced and these holes are accelerated so as to become the hot holes. Because the energy of the hot holes is very high, these holes can tunnel through the oxide layer. Thus, the current is typically caused by positive charges accumulated on the gate region of the device.
Referring to FIG. 5, it shows a voltage-time curve diagram of an NMOS device that an electrostatic discharge (ESD) pulse is applied. Besides, the gate of the NMOS device is floating and it is not coupled with any power line. During the experiment, the ESD pulse is input into the drain of an NMOS device, the floating voltage of the gate and the drain is simultaneously measured. Besides, the total width of the device is 150 or 400 micrometers. For the total width 150 micrometers NMOS under an HBM ESD pulse, the voltage on the drain and the gate is demonstrated in the curve A and B, respectively. For the total width 400 micrometers under an HBM ESD pulse, the floating voltage of the drain and the gate is presented in the curve C and D, respectively. During an ESD pulse is input into the drain, the gate is floating and the ESD pulse input into the drain is about 500 volt. After the voltage on the drain is drop down, the voltage on the gate still maintains at a positive level. That is, even an ESD pulse had been output from the drain, a positive voltage is still induced in the gate. Consequently, the phenomenon proves that the above theory is right. As an NMOS device is operated during the electrostatic discharge, the electrical holes accumulate in the gate to induce a positive voltage difference.
Referring to FIG. 6, it shows two voltage-time curve diagram of an NMOS device. An ESD pulse is input into the drain of an NMOS device and the gate of the NMOS device is floating. As the input ESD pulse is about 1000 volt and 1500 volt, the voltage of the gate is demonstrated by the curve A and the curve B according to FIG. 6, respectively. As mentioned in FIG. 6, after an ESD pulse input into an ESD protection device, the maximum voltage difference in the device could reach 16 volts and the period of the maximum is longer as the voltage pulse is higher. As the ESD voltage input into the device is about 1 kV, the period of the maximum voltage is about 3 nanoseconds. Furthermore, the ESD voltage input into the device is about 1.5 kV, the period of the maximum voltage is about 10 nanoseconds.
According to the above discussion, the ESD protective circuit using NMOS device has a band-to-band tunneling issue. When a positive voltage is applied on the gate of the NMOS device, the channel of the device is turned on and the static charges mainly flow out from the turn-on channel. The current will localize on the channel and that damages the device. Thus, a new ESD protective circuit is needed for preventing the NMOS device of the circuit from destroyed.